CELUG and Design Infrastructure Alley 2018 Speaking Schedule

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Come Shape The Future of IT Infrastructure for Semiconductor at DAC 2018!

Be sure to join us at DAC in San Francisco from June 24-28.  You will be able to get access to the Design Infrastructure Alley simply by registering using the “I Love DAC” promotionwhich gives you FREE access to the show floor!

Three Days of Insightful, Thought-Provoking Content on Engineering IT Infrastructure Topics

This year’s DAC will have the Design Infrastructure Alley, a section of DAC devoted to the infrastructure required to design chips and systems.  The premise for the DIA is pretty simple:

Every year we get together at DAC to talk about new tools and new methods to create more complex chips and systems.  But we never talk about the infrastructure needed to usethese new methods and tools.  The Design Infrastructure Alley bridges the gap between potential and execution and allows IT Professionals, Engineers and EDA Suppliers to have a conversation about how best to enable Design.

Below is the speaking schedule for this year’s Inaugural Design Infrastructure Alley.  We’re still working through some details regarding topic titles, and we do have one “surprise” guest which will be revealed soon.  All of these speakers will be at the Design on Cloud Pavilion on the main Exhibit Floor.  You can see the floorpan hereto know where you’re going in advance.

June 25
June 26
June 27
10:30-11:15Association of HPC Pros: Intro to DIAMetricsDell EMC: Peeling the onion: how enterprise storage limits tool performance and what you need to do to fix it
11:30-12:15Si2: Si2 OpenAccess—Design Infrastructure for the FutureAltair: Cloud for Cloud SkepticsPure Storage: Faster Time to Market: Eliminate Data Bottlenecks for EDA and AI Workloads
12:30-1:30Microsoft / AzureCadence: EDA on the Cloud: Are We Ready?FootPrintKu PalPilot: Influencing Design Libraries with Cloud Automation
1:30-2:15IC Manage: 10 minutes to Hybrid Cloud Bursting – Run Existing Workflows in the Cloud without RetoolingGoogleTI: CPU Oversubscription in Compute Clouds
2:30-3:15IBMUniva: Towards a Strategic Deployment Pattern for the EDA Hybrid CloudEllexus: Fast, Agile and Cloud Ready: How to make workflows faster and easier to move
3:30-4:15ACMAWS: Innovation at Cloud Speed for IoT, AI, and Semiconductor DesignAlibaba: Alibaba Eco-System Enable Your Business
4:30-5:30Panel - Cloud: Cloud Computing for EDA: Pie in the Sky or Pie in the FaceRescale: Revolutionizing semiconductor design workflows with HPC in the cloudSuSE

There will also be a CELUG Meeting, focusing specifically on license topics which will occur on Tuesday, June 26 in a separate room.  You must register for this conference separately, and the cost is only $100.  The agenda for the CELUG conference is still under construction, so there may be some minor changes to it.  Double-check this page to see the latest.

Special thanks to our friends at OpenIT for sponsoring lunch at the CELUG Conference!  Your generous donation is much appreciated!


9:00 - 9:30Ansys
9:30 - 10:00Mathworks
10:00 - 10:30Mentor Graphics, a Siemens Business
10:30 - 11:00 Cadence
11:00 - 11:30Synopsys
11:30 - 1:00Lunch Break
1:00 - 1:30Flexera, Flexnet Publisher
1:30 - 2:00Flexnet Manager for Engineering Applications
2:00 - 3:00Machine Certification Discussion
3:00 - 4:00CELUG Only Session

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